Non-volatile semiconductor memory device

ABSTRACT

When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a verification operation subsequent to a program operation by which a threshold voltage of a memory cell transistor to be written has become equal to or higher than a verification level for the first time is carried out twice or more at the same verification level, verification operations of the second and subsequent times are carried out after a second program operation which is carried out with the memory cell transistor set in an unselected state.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of priorityunder 35 U.S.C. §120 from U.S. Ser. No. 12/564,612, filed Sep. 22, 2009,and claims the benefit of priority from prior Japanese PatentApplication No. 2009-058362, filed Mar. 11, 2009, the entire contents ofeach of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile semiconductor memorydevice and, more particularly, to a write controller for carrying outwrite control of a memory cell.

2. Description of the Related Art

Among non-volatile semiconductor memories, a NAND flash memory is knownfor its capability to cope with an increasing memory capacity and highintegration. In a chip of the NAND flash memory, a plurality of NANDmemory cells (hereinafter referred to as NAND cells) is arranged in acell array area. Each of the NAND cells includes a plurality of memorycell transistors each having a stacked gate structure constituted of afloating gate and control gate, and connected in series, and selecttransistors connected to both ends of the plurality of memory celltransistors.

When data is written to the NAND cell, a system for carrying out controlin such a manner that a program operation and a verification operationare alternately repeated is used in order to narrow the distributionwidth of the threshold voltage of the memory cell transistors. Aplurality of the program operations and a plurality of the verificationsoperation are collectively called a write operation in some cases. Inthis case, the program operation is carried out in several times whilethe program voltage (Vpgm) is gradually stepped up. That is, the programoperation is carried out while the program voltage (Vpgm) is stepped up,and the verification operation is carried out after each programoperation. The verification operation implies an operation forconfirming whether or not the threshold voltage of the memory celltransistor could have been written (increased) to a target value. Inthis case, if the target value is not attained, the program operationand the verification operation are carried out again. On the other hand,if it is determined that the program has been carried out to the targetvalue, a voltage close to the power supply voltage is applied to a bitline BL connected to the NAND cell at the time of the next program, andthe channel of the memory cell transistor is brought into a boostedstate in order that the memory cell transistor in the unselected statecan be prevented from being additionally programmed.

It should be noted that normally, in order to allow a program margin tothe NAND cell, the reference level (verification level) for judging theread data at the time of the verification operation is set at a voltagehigher than the judgment reference level at the time of a normal readoperation to a certain degree.

However, due to the variation of the process and the circuit, the amountof change in the threshold voltage of the memory cell transistor becomesnon-proportional with respect to a step-up in the program voltage(dVpgm), and the write operation may be terminated at a value lower thanthe target value in some cases. As a result of this, it becomesimpossible to keep the threshold voltage within the target thresholdvoltage distribution width, and thus the reliability and performance aredeteriorated. If it is intended to allow a margin for the lowering ofthe threshold voltage due to the above variation, the write operationmust be carried out until a higher threshold voltage is obtained,leading to the other problem such as lowering of the yield.

It should be noted in U.S. Pat. No. 6,643,188, Tanaka et al., it isdisclosed that a verification circuit for confirming the state of thememory cell after a write operation, and a data update circuit forupdating the contents of a write data circuit to carry out rewrite to amemory cell insufficiently written on the basis of the contents of thewrite data circuit, and state of the memory cell after the writeoperation are provided, and the write operation based on the contents ofthe write data circuit, a write verification operation, and update ofthe contents of the write data circuit are repeated until the memorycell is brought into a predetermined written state.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda non-volatile semiconductor memory device, comprising:

a memory cell array in which a plurality of memory cell transistors arearranged; and

a write controller configured to control in a write operation that averification operation subsequent to a program operation is carried outwith a program voltage increasing stepwise for each program operation,

wherein the write controller controls that a first verificationoperation is carried out at a first verification level for a memory celltransistor to be written, subsequently to the first verificationoperation, a program operation is carried out with the memory celltransistor set in an unselected state, and a verification operation forthe memory cell transistor subsequent to the program operation iscarried out as a second verification operation at the first verificationlevel.

According to a second aspect of the present invention, there is provideda non-volatile semiconductor memory device, comprising:

a memory cell array in which a plurality of memory cell transistors arearranged; and

a write controller configured to control in a write operation that averification operation subsequent to a program operation is carried outwith a program voltage increasing stepwise for each program operation, ahalf-select write operation is carried out in a half-selected statewhere a given intermediate voltage lower than the power supply voltageis applied to a bit line connected to the memory cell transistor, and afirst verification level, and a second verification level lower than thefirst verification level are set,

wherein the write controller controls that a program operationsubsequent to a first program operation that is a program operation bywhich a threshold voltage of a memory cell transistor to be written hasbecome equal to or higher than the second verification level for thefirst time is carried out as a second program operation by thehalf-select write operation, a verification operation subsequent theretois carried out as a first verification operation by using the firstverification level as a point of reference, further a third programoperation is carried out with the memory cell transistor to be writtenset in an unselected state, and a verification operation subsequentthereto is carried out as a second verification operation by using thefirst verification level as the point of reference.

According to a third aspect of the present invention, there is provideda non-volatile semiconductor memory device, comprising:

a memory cell array in which a plurality of memory cell transistors arearranged; and

a write controller configured to control in a write operation that averification operation subsequent to a program operation is carried outwith a program voltage increasing stepwise for each program operation, ahalf-select write operation is carried out in a state where apredetermined intermediate voltage lower than the power supply voltageis applied to a bit line connected to the memory cell transistor, and afirst verification level, and a second verification level lower than thefirst verification level are set,

wherein the write controller controls that a verification operationsubsequent to a program operation carried out for a memory celltransistor subsequently to a program operation by which a thresholdvoltage of the memory cell transistor of a write object has become equalto or higher than the second verification level for the first time iscarried out by using the first verification level as a point ofreference, and if the verification operation fails, a program operationis carried out by a half-select write operation to be carried out in ahalf-selected state where a given intermediate voltage lower than thepower supply voltage is applied to a bit line connected to the memorycell transistor.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram of a NAND flash memory according to anembodiment of the present invention;

FIG. 2 is a block circuit diagram schematically showing extracted partof a core part of the memory of FIG. 1;

FIG. 3 is a block diagram schematically showing one set of a senseamplifier and data latch circuit extracted from FIG. 2;

FIG. 4 is a view showing the threshold voltage distribution state causedby the influence of noise of the memory cell transistors;

FIG. 5 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a first embodiment;

FIG. 6 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a second embodiment;

FIG. 7 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a third embodiment;

FIG. 8 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a fourth embodiment;

FIG. 9 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a fifth embodiment;

FIG. 10 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a sixth embodiment;

FIG. 11 is a characteristic diagram showing an example of a relationshipbetween the step-up of the program voltage and threshold voltage of thememory cell transistor; and

FIG. 12 is a characteristic diagram showing an example of each of anideal threshold voltage distribution width and actual threshold voltagedistribution width of the memory cell transistors.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be described below by way of variousembodiments with reference to the accompanying drawings. In thedescription, parts common throughout all the drawings will be denoted bycommon reference symbols.

FIG. 1 is a block diagram showing the schematic configuration of a NANDflash memory according to an embodiment of the present invention. FIG. 2is a block circuit diagram schematically showing extracted part of thecore part of a memory of FIG. 1.

The NAND flash memory is configured to include a memory cell array 1,row decoder 2, sense amplifier & data latch group 3, internal voltagegeneration circuit 4, control circuit 5, address register 6, columndecoder 7, interface circuit 8, and the like.

The memory cell array 1 is divided into a plurality of memory cellblocks BLK0 to BLKm as shown in FIG. 2. In each of the memory cellblocks BLK0 to BLKm, a plurality of NAND cells are arranged in a matrixform. The NAND cells are formed in such a manner that a plurality ofmemory cell transistors adjacent to each other are connected in seriesto share a source and a drain with each other. Each of drains on one endside of the NAND columns is connected to each of bit lines BL0 to BLnthrough each of a plurality of first select transistors. Each of sourceson the other end side of the NAND columns is connected to a cell sourceline SL as common connection through each of a plurality of secondselect transistors. Each of select gate lines SGS and SGS provided toextend in the row direction of the memory cell array 1 is connected to agate of each of first and second select transistors of the same rows,respectively as common connection. Each of a plurality of word lines WL0to WLn+1 provided to extend in the row direction of the memory cellarray 1 is connected to a control gate of each of memory celltransistors of the same rows. Here, a plurality of memory celltransistors connected to one word line constitute one page, and memorycell transistors of the number corresponding to a plurality of pagesconstitute one block of the memory cell blocks BLK0 to BLKm. It shouldbe noted that writing or reading to or from the memory cell array 1 iscarried out in units of pages, and erasing is carried out in units ofblocks.

In this embodiment, as shown in FIG. 3, one sense amplifier & data latch30 provided in the sense amplifier & data latch group 3 is connected toeach of the bit lines BL (BL0 to BLn) through a column select transistorcontrolled by a select signal BLS. Here, a column select signal lineBLSO is connected to a gate of a column select transistor of an oddnumber column, and a column select signal line BLSE is connected to agate of a column select transistor of an even number column. At the timeof a write operation, the sense amplifier & data latch group 3 latchesdata corresponding to one page of cell data (program data) to bewritten. Further, at the time of read, the sense amplifier & data latchgroup 3 latches data corresponding to one page of cell data read out toeach bit line from a selected memory cell block BLK0 to BLKm in thememory cell array 1.

To the interface circuit 8, various commands, a row address signal, celldata to be written, and the like are input, each of address signals (rowaddress signal and column address signal) Add is supplied to the addressregister 6 to be latched therein, and a command Com is supplied to thecontrol circuit to be latched therein. Further, the interface circuit 8is supplied with data Data read from the memory cell array 1, andlatched by the sense amplifier & data latch group 3 through a data line10, and outputs the data Data.

The control circuit 5 includes a command register, command decoder,status register, and the like, and various control signals (a chipenable signal/CE, command latch enable signal CLE, address latch enablesignal ALE, write enable signal/WE, read enable signal/RE, and the like)are input thereto from outside. The command register latches commanddata, and command decoder decodes a supplied command to determine anoperation mode of the flash memory, and generate control signals forcontrolling an overall operation of the flash memory in accordance withthe operation mode. On the basis of these control signals, a readoperation, a write operation, an erase operation, and a verificationoperation of each circuit in the memory, the internal voltage generationcircuit 4, and the like are controlled.

The internal voltage generation circuit 4 generates internal voltages onthe basis of the control signals. For example, at the time of the writeoperation, the internal voltage generation circuit 4 generates highvoltages such as a program voltage, a transfer voltage, and the like,and supplies the voltages to the row decoder 2 and memory cell array 1.

A row address signal (block address signal, page address signal) latchedby the address register 6 is supplied to the row decoder 2 together withthe operation mode signal, and is decoded therein. The row decoder 2selects a memory cell block BLK0 to BLKm, and a page in the memory cellarray 1, and controls the potentials of the word lines WL0 to WLn+1, andselect gate lines SGD and SGS in the selected block. Further, a columnaddress signal latched by the address register 6 is supplied to thecolumn decoder 7 to be decoded. The column decoder 7 selects a column ofthe memory cell array 1 on the basis of the column address signal.

FIG. 3 is a block diagram schematically showing one sense amplifier &data latch 30 extracted from the sense amplifier & data latch group 3 inFIG. 2. In the sense amplifier & data latch 30, a sense amplifier (S/A)31 is connected to a bit line BL through a column select transistor, andis connected to a data latch (DLSA) 32 which is a data latch on thesense amplifier side. The data latch 32 retains data forcharging/discharging the bit line BL, or data sensed by the senseamplifier.

Further, a data latch 34 constituted of a plurality of latches (in thisexample four latches DL1, DL2, DL3, and DL4) is connected to the senseamplifier 31 through a data arithmetic circuit 33. As for the number oflatches in the data latch 34, when information of n bits (n is aninteger equal to or larger than 2) is programmed in one memory cell inthe memory cell array, at least n latches are required to store programdata supplied from an external bus. In this example, two latches (DL1,DL2) required to carry out a program of 2 bits/cell, and further twolatches (DL3, DL4) required to retain a determination result (flag) ofthe data arithmetic circuit 33 are shown. It should be noted that when aprogram of 1 bit/cell is to be carried out, the number of the latchesmay be three (DL1, DL2, DL3). The data arithmetic circuit 33 is providedwith a write control function to be described below.

Here, an operation of the sense amplifier & data latch group 3 of FIG. 3will be described below. Program data supplied from the external bus isinput to the latches DL1, DL2 in the data latch 34. The data arithmeticcircuit 33 carries out control to determine at which of 0 V (Vss),Vinhibit to be described later, and VQPW to be described later thepotential Vb1 of the bit line BL connected to the sense amplifier & datalatch 30 is to be set on the basis of the program data, transfer adetermination result to the data latch 32, and further transfer the dataof the data latch 32 to the sense amplifier 31.

As shown in FIG. 2, control gates of memory cell transistors in the samerow are connected to any one of the word lines WL0 to WLn+1 as commonconnection, and at the time of the write operation, the memory celltransistors in the same row are simultaneously subjected to the writeoperation. In this case, in a memory cell transistor with a high writespeed, the number of program loops required until the write operation tothe target threshold voltage is completed is small. Conversely, in amemory cell with a low write speed, a large number of program loops arerequired until the write operation to the target threshold voltage iscompleted.

FIG. 4 is a view showing the threshold voltage distribution state of thememory cell transistors to explain the influence of the variation at thetime of the write operation to the NAND cell. In the NAND flash memory,the write operation is terminated at a value lower than the targetthreshold voltage Vth [V] in some cases as shown by a broken line inFIG. 4 due to the variation of the process and the circuit.

Thus, in the present invention, as will be described in the followingexample, at the time of the write operation, the control circuit 5controls the overall circuit to repeat the verification operation aplurality of times. As a result of this, even when the write operationis terminated at a low threshold voltage as it is during a firstverification operation due to the influence of the variation, it becomespossible to be hardly influenced by the variation, and keep thethreshold voltage within the target threshold voltage distribution widthas shown by a solid line in FIG. 4. Various embodiments will bedescribed below with respect to the program operation and theverification operation.

First Embodiment

FIG. 5 is a timing chart showing program operations and verificationoperations in the NAND flash memory according to a first embodiment. Inthis embodiment, a verification operation is carried out twice or moreat the same verification level after a program (PRG) operation (firstprogram operation) by which the threshold voltage of the memory celltransistor to be written has reached the verification level for thefirst time, while the program voltage (Vpgm) applied to a control gateof a memory cell transistor which is selected by any one of the wordlines WL0 to WLn+1 is stepped up. In this case, the verificationoperations of the second and subsequent times are carried out after theprogram operation (second program operation) subsequent to the firstprogram operation, and the program operation and the verificationoperation are repeated until the verification operation passes (thethreshold voltage of the memory cell transistor to be written becomesequal to or higher than the verification level).

That is, as shown by the bit line potential Vbl(a) in FIG. 5, if a firstverification operation (V1) carried out after the nth (nth loop) programoperation of the program loop has completed, the program operation ofthe (n+1)th loop is carried out after bringing the channel of the memorycell transistor to be written into the boosted state (the state where noprogram occurs, i.e., the unselected state) by applying a select inhibitvoltage (inhibit voltage: about 3.0 V) to the bit line BL.

After this, a second verification operation (V2) is carried out, and ifthe verification operation (V2) has also passed like the verificationoperation (V1), a program operation is not carried out thereafter.Conversely, if the verification operation (V2) of the (n+1)th loop hasfailed, a program operation (PRG) is carried out again for the (n+2)thloop as shown by the bit line potential Vbl(b) in FIG. 5. Likewise, ifthe verification operation (V2) successively fails in the (n+1)th loopand (n+2)th loop, the program operation and the verification operationare repeated until the verification operation (V2) passes as shown bythe bit line potential Vbl(c) in FIG. 5. It should be noted that in thisembodiment, although the verification operation subsequent to the firstprogram operation is carried out twice, the number of times of theverification operation subsequent to the first program operation may beincreased to three times or more as the need arises.

As described above, in the first embodiment, in the NAND flash memoryprovided with the control circuit 5 for carrying out control, at thetime of writing data to the NAND cell, in such a manner that theverification operation subsequent to the program operation is carriedout while the write voltage is increased stepwise for each programoperation, the control circuit 5 carries out control to repeat theprogram operation and the verification operation subsequent theretountil the verification operations of the second and subsequent times tobe carried out after the first program operation passes. That is, thecontrol circuit 5 carries out control in such a manner that theverification operation subsequent to the first program operation iscarried out twice or more at the same verification level, and theverification operations of the second and subsequent times are carriedout after the second program operation. Further, control is carried outin such a manner that if the second verification operation subsequent tothe second program operation has passed, the write operation isterminated, and if the second verification operation subsequent to thesecond program operation has failed, a program operation and averification operation are repeated until the verification operationpasses.

By virtue of such control, even if the write operation is terminated ata value lower than the target threshold voltage due to the variation ofthe process and the circuit at the time of the first program operation,it becomes possible to write an appropriate threshold voltage in theprogram operation subsequent to the second verification operation and inthe verification operation. Consequently, it is possible to improve thethreshold voltage distribution width of the memory cell transistorsshown by a solid line in FIG. 4, and prevent defective write fromoccurring.

Second Embodiment

FIG. 6 is a timing chart showing program operations and verificationoperations in a NAND flash memory according to a second embodiment. Asshown by the bit line potential Vbl(a) in FIG. 6, if a firstverification operation (V1) carried out after a program operation (firstprogram operation) of the nth loop has completed as in the firstembodiment, a program operation (second program operation) of the(n+1)th loop is carried out in the unselected state, and thereafter asecond verification operation (V2) is carried out. If the secondverification operation (V2) has passed like the first verificationoperation (V1), no program operation is carried out thereafter.

If, although the first verification operation (V1) has passed at the nthloop, the second verification operation (V2) has failed at the (n+1)thloop, a program operation is carried out at the (n+2)th loop as shown bythe bit line potential Vbl(b) in FIG. 6. At this time, the programvoltage (Vpgm) has already been stepped up twice with respect to the nthloop, and hence there is a strong possibility of the next verificationoperation to pass. Accordingly, in this embodiment, as for the memorycell transistor in which the second verification operation (V2) hasfailed at the (n+1)th loop, the write operation is carried out at the(n+2)th loop, and thereafter the write operation is terminated withoutcarrying out a verification operation.

As described above, in the second embodiment, in addition to theobtained effect identical with that of the first embodiment, if thesecond verification operation fails, the verification operation to becarried out after the next program operation is skipped to terminate thewrite operation, and hence it is possible to make the number ofverification operations less than in the first embodiment, and make thewrite speed higher than in the first embodiment.

Third Embodiment

FIG. 7 is a timing chart showing program operations and verificationoperations in a NAND flash memory according to a third embodiment. Thisembodiment is an example in which a method (quick-pass write [QPW]) ofcontrolling the threshold voltage distribution width of memory celltransistors narrow by carrying out half-select write by applying ahalf-select voltage to the bit line BL at the time of the programoperation is used in combination with the normal method. Here, thehalf-select write implies a system in which an intermediate voltage(e.g., 1 V) between 0 V and a voltage close to the power supply voltageis applied to the bit line BL to carry out writing. In the normalprogram operation, 0 V is applied to a bit line BL for carrying outwriting, and a voltage close to the power supply voltage, for example, 3V is applied to a bit line not for carrying out writing. However, in theQPW, an intermediate voltage of about 1 V is applied to the bit line atthe time of the program operation, whereby an effect of providing afeeling that as if the step change voltage (dVpgm) of the programvoltage has become smaller in a pseudo manner is obtained.

As shown by the bit line potential Vbl(a) in FIG. 7, after a programoperation (first program operation) of the nth loop, a verificationoperation (VL) is carried out by using a verification low level (secondverification level) lower than the normal verification level (firstverification level) as the point of reference. Here, the verificationlow level is lower than the normal verification level by, for example,about half the step change voltage dVpgm of a program voltage at thetime of the normal program operation. If the verification operation haspassed, a program operation (second program operation) of the (n+1)thloop is carried out by applying a voltage of about 1 V to the bit lineBL, and by using the QPW in the half-selected state.

Thereafter, a first verification operation (V1) is carried out by usingthe normal verification level as the point of reference, and if thefirst verification operation (V1) has passed, a program operation (thirdprogram operation) of the (n+2)th loop is carried out in the unselectedstate, thereafter a second verification operation (V2) is carried out byusing the normal verification level as the point of reference. If thesecond verification operation has also passed like the firstverification operation (V1), no program operation is carried outthereafter. The bit line potential Vbl(a) in FIG. 7 shows an example inwhich after the verification operation (VL) at the verification lowlevel has passed, the first verification operation (V1) has also passedby the program operation carried out once. However, if the firstverification operation (V1) fails, the second program operation and thefirst verification operation are carried out until the firstverification operation (V1) passes.

Further, if the second verification operation (V2) of the (n+2)th loopfails, as shown by the bit line potential Vbl(b) in FIG. 7, ahalf-select write operation is carried out at the (n+3)th loop, and thenthe second verification operation (V2) is carried out again. If thissecond verification operation (V2) fails again, the program operation(half-select write operation) and second verification operation arerepeated until the second verification operation (V2) passes. Althoughthe bit line potential Vbl(b) in FIG. 7 shows an example in which thesecond verification operation (V2) passes by an additional programoperation carried out once, actually the program operation (half-selectwrite) and second verification operation are repeated over and overagain until the second verification operation (V2) passes.

As described above, in the third embodiment, when the half-select writeoperation is carried out, the verification operation subsequent to theprogram operation is carried out once at the verification low level, andtwice or more at the normal verification level. Further, as for a cellin which the verification operations of the second and subsequent timesfail, it is conceivable that the write operation has not been carriedout at the target threshold voltage due to the influence of noise, andthere is the possibility of the cell being brought into an overprogramming state at the next program due to the enhanced electricfield, and increased speed. In such a case, it is possible to preventthe cell from being brought into the over programming state by carryingout the next program operation by the half-select write operation tomake a write speed slow.

According to the third embodiment, in addition to the obtained effectidentical with that of the first embodiment, it is possible to realize afurther narrowed threshold voltage distribution width of the memory celltransistors by combining the half-select write operation for narrowingthe threshold voltage distribution width of the memory cell transistors,and the write operation for the anti-variation measures.

Fourth Embodiment

FIG. 8 is a timing chart showing program operations and verificationoperations in a NAND flash memory according to a fourth embodiment. Asshown by the bit line potential Vbl(a) in FIG. 8, like in the thirdembodiment, after a program operation (first program operation) of thenth loop, a verification operation (VL) using the verification low levelas the point of reference is carried out, and if the verificationoperation (VL) passes, a program operation (second program operation) ofthe (n+1)th loop is carried out by the half-select by applying a voltageof about 1 V to the bit line BL. Thereafter, a first verificationoperation (V1) using the normal verification level as the point ofreference is carried out, then even if the first verification operation(V1) passes, a program operation (third program operation) of the(n+2)th loop is carried out in the unselected state, and thereafter asecond verification operation (V2) also using the normal verificationlevel as the point of reference is carried out. If the secondverification operation (V2) also passes like the first verificationoperation (V1), thereafter no program operation is carried out.

If the verification operation (VL) passes at the nth loop, further thefirst verification operation (V1) passes at the (n+1)th loop, and thesecond verification operation (V2) of the (n+2)th loop fails, as shownby the bit line potential Vbl(b) in FIG. 8, the half-select writeoperation is carried out at the (n+3)th loop. At this time, the programvoltage Vpgm has already been stepped up twice with respect to the nthloop, and there is a strong possibility of the verification passing.Accordingly, in this embodiment, with respect to the memory celltransistor in which the second verification operation (V2) of the(n+2)th loop has failed, after the half-select write operation iscarried out at the (n+3)th loop, no verification operation is carriedout, and the write operation is terminated.

As described above, in the fourth embodiment, in addition to theobtained effect identical with that of the third embodiment, if theverification operations of the second and subsequent times fail, theverification operation to be carried out after the next programoperation is skipped, and the write operation is terminated, whereby thenumber of verification operations can be reduced, and the write speedcan be increased as compared with the third embodiment.

FIG. 11 is a characteristic diagram showing an example of a relationshipbetween the step-up of the program voltage (Vpgm), and the thresholdvoltage (Vth) of the memory cell transistor. FIG. 12 is a characteristicdiagram showing an example of a state where the actual threshold voltagedistribution (broken line) changes (widens) with respect to the idealthreshold voltage distribution (solid line) due to the variation in thestep-up of the threshold voltage (Vth) of the memory cell transistor forthe step-up of the program voltage (Vpgm).

In the ideal case, as shown by the solid line in FIG. 11, the thresholdvoltage of the memory cell transistor increases in proportion to thestepwise increase in the program voltage. However, in the actual case, aprogram operation is quickly carried out or slowly carried out for eachstep due to the variation of the process and the circuit. As can be seenfrom the characteristic shown in FIG. 12, at the time of the programoperation at a certain program voltage, if an amount of increase in thethreshold voltage is smaller than the step-up change amount (dVpgm), andif the next program operation is carried out by stepping up the programvoltage, the electric field applied to the tunnel oxide film isenhanced, and hence there is a strong possibility of the increase in thethreshold voltage varying more largely than the dVpgm. Fifth and sixthembodiments contrived to improve the above drawback will be describedbelow.

Fifth Embodiment

FIG. 9 is a timing chart showing program operations and verificationoperations in a NAND flash memory according to a fifth embodiment. Asshown by the bit line potential Vbl(a) in FIG. 9, a verificationoperation (VL) is carried out after a program operation of the nth loop.Here, the verification low level of the verification operation (VL) isset at a level lower than the target threshold voltage by, for example,half the step-up change amount (dVpgm). If this verification operation(VL) passes, a program operation (first program operation) of the(n+1)th loop is carried out, and thereafter a verification operation (V)using the normal verification level as the point of reference is carriedout. If the verification operation (V) passes like the verificationoperation (VL), thereafter no program operation is carried out.

However, if although the verification operation (VL) of the nth looppasses, the verification operation (V) of the (n+1)th loop fails, asshown by the bit line potential Vbl(b) in FIG. 9, there is a strongpossibility of the threshold voltage variation being smaller than thestep-up change amount (dVpgm), and the threshold voltage varying morelargely than the step-up change amount at the next program operation ofthe (n+2)th loop, and hence a write speed is made slow by applying ahalf-select voltage (for example, 1 V) to the bit line BL at the time ofthe program operation. Here, although the verification operation (V)passes at the (n+2)th loop, actually, a program operation and averification operation by the half-select voltage are repeated until theverification operation (V) passes.

As described in the fifth embodiment, a verification low level lowerthan the normal verification level by, for example, half the dVpgm isset, and if the verification operation (VL) using the verification lowlevel as the point of reference passes, and the verification operation(V) subsequent to the next program operation fails, then the half-selectwrite operation and the verification operation are repeated. As a resultof this, it is possible to prevent the high voltage side of thethreshold voltage distribution of the memory cell transistors from beingwidened by the influence of the variation, and obtain the thresholdvoltage distribution shown by a solid line in FIG. 12.

Sixth Embodiment

FIG. 10 is a timing chart showing program operations and verificationoperations in a NAND flash memory according to a sixth embodiment. Asshown by the bit line potential Vbl(a) in FIG. 10, a verificationoperation (VL) is carried out after a program operation of the nth looplike in the fifth embodiment. If the verification operation (VL) passes,a verification operation (V) is carried out after a program operation ofthe (n+1)th loop is carried out. If the verification operation (V) alsopasses like the verification operation (VL), thereafter no programoperation is carried out.

Conversely, if, although the verification operation (VL) of the nth looppasses, the verification operation (V) of the (n+1)th loop fails, asshown by the bit line potential vbl(b) in FIG. 10, there is a strongpossibility of the write operation being terminated at the programoperation of the (n+2)th loop, hence half-select write operation iscarried out at the (n+2)th loop, thereafter the verification operationis skipped, and then the write operation is terminated.

As described above, in the sixth embodiment, in addition to the obtainedeffect identical with that of the fifth embodiment, if the verificationoperation (V) fails, then the half-select write operation is carried outonce, a verification operation is skipped, then the write operation isterminated, and hence it is possible to increase the write speed ascompared with the fifth embodiment.

Next, the operation of the sense amplifier & data latch 30 in FIG. 3 ineach of the above embodiments will be described below.

(Operations of First and Second Embodiments)

First, a program operation and verification operation (V1) are carriedout in accordance with the data input to the latches DL1, DL2. If theverification operation (V1) passes, binary 0 is written to the latch DL4as a flag. Then, if data is present in each of the latches DL1, DL2, andDL4 (binary 0), a program operation is skipped, and a verificationoperation (V2) is carried out. If the verification operation (V2)passes, all the latches DL1,

DL2, and DL3 are made binary 1 (erased) to terminate the writeoperation, and if the verification operation (V2) fails, binary 0 iswritten to the latch DL3. If no data is present in all the latches DL1,DL2, and DL4 (binary 1), no further write operation is carried out.

Then, if data is present in each of the latches DL1, DL2, DL3, and DL4,in the first embodiment, the program operation and the verificationoperation (V2) are carried out until the verification operation (V2)passes. On the other hand, in the second embodiment, only the programoperation is carried out once, then each of the latches DL1, DL2, DL3,and DL4 is made binary 1, and the write operation is terminated.

(Operations of Third and Fourth Embodiments)

First, a program operation and verification operation (VL) are carriedout in accordance with the data of the latches DL1, DL2. If theverification operation (VL) passes, binary 0 is written to the latch DL3as a flag. Then, if data is present in each of the latches DL1, DL2, andDL3, after carrying out a program operation (half-select writeoperation) by applying a half-select voltage to the bit line BL, averification operation (V1) is carried out. If the verificationoperation (V1) passes, the latch DL3 is made binary 1 to erase the latchDL3, and binary 0 is written to the latch DL4. Then, if data is presentin each of the latches DL1, DL2, and DL4, the program operation isskipped, and a verification operation (V2) is carried out. If theverification operation (V2) passes, each of the latches DL1, DL2, andDL4 is made binary 1 to terminate the write operation, and if theverification operation (V2) fails, binary 0 is written to the latch DL3.If no data is present in all the latches DL1, DL2, and DL4, no furtherwrite operation is carried out.

Then, if data is present in each of the latches DL1, DL2, DL3, and DL4,in the third embodiment, the program operation and the verificationoperation (V2) are carried out until the verification operation (V2)passes. On the other hand, in the fourth embodiment, only the programoperation is carried out once, and each of the latches DL1, DL2, DL3,and DL4 is made binary 1, and the write operation is terminated.

(Operations of Fifth and Sixth Embodiments)

First, a program operation and verification operation (VL) are carriedout in accordance with the data of the latches DL1, DL2. If theverification operation (VL) passes, binary 0 is written to the latch DL4as a flag. Then, if data is present in the latches DL1, DL2, and DL4, aprogram operation and verification operation (V) are carried out. If theverification operation (V) passes, each of the latches DL1, DL2, and DL4is made binary 1 to terminate the write operation, and if theverification operation (V) fails, binary 0 is written to the latch DL3.If no data is present in all the latches DL1, DL2, and DL4, no furtherwrite operation is carried out.

Then, if data is present in each of the latches DL1, DL2, DL3, and DL4,in the fifth embodiment, the program operation and the verificationoperation (V) are carried out until the verification operation (V)passes. On the other hand, in the sixth embodiment, only the programoperation is carried out once, then each of the latches DL1, DL2, DL3,and DL4 is made binary 1, and the write operation is terminated.

It should be noted that the operations in the first, second, third, andfourth embodiments described previously are enabled even if, in FIG. 2,the configuration is changed to a configuration in which a plurality ofbit lines BL share one sense amplifier & data latch 30 with each other.

It should be noted that although in each of the above embodiments, thecase where the present invention is applied to a NAND flash memory hasbeen described, the present invention can also be applied to othernon-volatile semiconductor memories such as a NOR flash memory, and thelike in some cases, and can be appropriately modified and implementedwithin the scope not deviating from the gist of the invention.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A non-volatile semiconductor memory device comprising: a memory cellarray in which a plurality of memory cell transistors are arranged; anda write controller configured to control in a write operation that averification operation subsequent to a program operation is carried outwith a program voltage increasing stepwise for each program operation,wherein the write controller controls that a first verificationoperation is carried out at a first verification level for a memory celltransistor to be written, subsequently to the first verificationoperation, a program operation is carried out with the memory celltransistor set in an unselected state, and a verification operation forthe memory cell transistor subsequent to the program operation iscarried out as a second verification operation at the first verificationlevel.